1. Field of the Invention
The present invention relates to a bus-hold circuit for controlling the voltage on a pin of an in-system programmable logic device during both set-up and normal operation of the device.
2. Discussion of Related Art
In-system programmable logic devices (ISPLDs) are integrated circuit chips which are typically installed on a printed circuit board with other integrated circuit chips. The programmable logic of the ISPLD can be, for example, a field programmable gate array (FPGA) or complex programmable logic device (CPLD). ISPLDs typically operate in two distinct modes, namely, a set-up mode and a normal operating mode. The set-up mode includes two sub-modes. One sub-mode is a non-programmed sub-mode, in which the logic of the ISPLD has not yet been configured (i.e., not yet programmed). The second sub-mode is a configuration sub-mode, during which the logic of the ISPLD is configured (i.e., programmed) in accordance with conventional techniques. During the normal operating mode, the ISPLD has already been configured, and the ISPLD is receiving input signals and providing output signals to external devices in accordance with the particular configuration of the ISPLD.
The configuration sub-mode can be entered while the ISPLD is `in-system`. That is, the ISPLD can be configured while connected to other integrated circuit chips in the system. As a result, .ISPLDs provide operating flexibility.
Conventional ISPLDs include input/output (I/O) pins. Within some ISPLDs, each of the I/O pins is connected to an associated bus-hold circuit. Within other ISPLDs, each of the I/O pins is connected to an associated pull-up resistor circuit. Bus-hold circuits and pull-up resistor circuits prevent the I/O pins from being in a floating state. A floating state is defined as a state in which a pin is not connected to any of the supply voltages of the circuit. As a result, the logic state of a pin is indeterminate while the pin is in a floating state. As described in more detail below, both pull-up resistor circuits and bus-hold circuits have deficiencies.
FIG. 1 is a schematic diagram of a conventional bus-hold circuit 100 which is coupled to an I/O pin 101, an input stage 102 and an output stage 103 of an ISPLD. In the illustrated diagram, input stage 102 is a CMOS inverter and output stage 103 is a tri-stateable CMOS inverter. The bus-hold circuit 100 includes cross-coupled CMOS inverters 104-105 and resistor 106. During normal operation of bus-hold circuit 100, inverters 104 and 105 operate as a latch to store the state of the last signal applied to pin 101.
The state of the signal provided by bus-hold circuit 100 cannot be guaranteed when the ISPLD is in the set-up mode. That is, bus-hold circuit 100 may provide either a logic high signal or a logic low signal to I/O pin 101 (in response to signals provided to the bus-hold circuit) when the ISPLD has not yet been configured, or when the ISPLD is being configured. If the ISPLD is connected to other integrated circuit chips on a printed circuit board at this time, such an output signal can cause these other integrated circuit chips to operate in an undesired manner. For example, a signal having a particular logic state provided at an I/O pin of the ISPLD could instruct an attached integrated circuit chip to launch a missile.
As previously mentioned, other ISPLDs have I/O pins which are coupled to pull-up resistor circuits. A conventional pull-up resistor circuit includes a resistor coupled between the I/O pin and the Vcc voltage supply rail. The pull-up resistor circuit therefore holds the I/O pin at a logic high voltage (i.e., Vcc) when the ISPLD is in the set-up mode. As a result, the I/O pin (which is defined to have an active low output), does not drive any external circuits when the ISPLD is in the set-up mode.
However, problems can arise when using a pull-up resistor circuit with an I/O pin, especially when the pin is coupled to a tri-state bus. FIG. 2 is a schematic diagram of a conventional pull-up resistor circuit 200 which includes pull-up resistor 201 connected to Vcc voltage supply rail 202. Pull-up resistor 201 is also connected to a line which extends between I/O pin 203, input stage 204 and output stage 205. Input stage 204 is a CMOS inverter, and output stage 205 is a tri-stateable CMOS inverter in the described example. Pull-up resistor circuit 200, I/O pin 203 and input stage 204 are part of an ISPLD 206.
When ISPLD 206 is in the set-up mode, pull-up resistor 201 causes I/O pin 203 to be maintained at a well-defined logic high level (i.e., Vcc). However, as described in more detail below, pull-up resistor 201 causes problems in the normal operating mode when I/O pin 203 is coupled to a tri-state bus.
As further illustrated in FIG. 2, I/O pin 203 is connected to a tri-state bus 210. Tri-state bus 210 is controlled to be in one of three states, namely, a high voltage state, a low voltage state or a high-impedance state (i.e., tri-state). Tri-state bus 210 is controlled by input driver circuit 211 and capacitor 212. Other CMOS devices 221 and 222 are also connected to tri-state bus 210.
Tri-state bus 210 is placed in the high voltage state by applying a logic low output enable (OE bar) signal and a logic high data (D) signal to driver circuit 211. The logic low OE bar signal enables driver circuit 211 to pass the logic high data signal to tri-state bus 210.
Tri-state bus 210 is placed in the low voltage state by applying a logic low OE bar signal and a logic low data signal to driver circuit 211. The logic low OE bar signal enables driver circuit 211 to pass the logic low data signal to tri-state bus 210.
Tri-state bus 210 is placed in the high-impedance state by applying a logic high OE bar signal to driver circuit 211. Driver circuit 211 is disabled by the logic high OE bar signal, thereby preventing driver circuit 211 from asserting any voltage on tri-state bus 210.
During normal operation, tri-state bus 210 may transition from a low voltage state to a high-impedance state. When tri-state bus 210 enters the high-impedance state from the low voltage state, pull-up resistor 201 begins to raise the voltage on tri-state bus 210 from the low voltage state to Vcc. Because tri-state bus 210 is heavily loaded, the resultant rise time of the bus voltage can be very large (e.g., up to the order of one millisecond). This rise time is undesirable because CMOS circuits 221 and 222 will have their input voltages slowly swept through their trip points simultaneously, thereby resulting in excessive current.
It would be desirable to have an ISPLD which maintains the I/O pins of an ISPLD in a well-defined state while the ISPLD is in the set-up mode, and which maintains the I/O pins of an ISPLD in their last driven state when the ISPLD is in the normal operating mode.